1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a column select circuit for minimizing load to data input/output lines of a semiconductor device, a semiconductor memory device having the same, and a method of arranging the column select circuits in the semiconductor memory device.
2. Description of the Related Art
In general, approaches to improving performance of computer systems include improving the operational speed of the central processing unit (CPU) as well as the performance of memory devices that store data or programs required by the CPU. To improve the performance of the memory device, the bandwidth per unit time should be increased. The bit line data of a memory cell is selectively transferred to the data input/output lines through data input/output circuits, depending on the number of data input/output lines. Generally, the amount of data read from or written to the memory in a given time period, i.e., the bandwidth, directly depends on the number of data input/output lines.
The memory cell data loaded onto the data input/output lines of a semiconductor memory device determines the operational speed of the device. The operational speed of the semiconductor memory device is determined by the time between sensing the data stored in the memory cell to be read and outputting the data to the data input/output lines, or the duration required to transmit data to be written from the data input/output lines to the memory cell. Thus, the load applied to the data input/output lines should be reduced in order to prevent the operational speed of the semiconductor memory device from being reduced. The data input/output lines are connected to column select circuits, and thus a column select circuit should be able to minimize the load to the data input/output lines.